Microchip Technology /ATSAMD51N19A /OSCCTRL /INTENSET

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Interpret as INTENSET

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (XOSCRDY0)XOSCRDY0 0 (XOSCRDY1)XOSCRDY1 0 (XOSCFAIL0)XOSCFAIL0 0 (XOSCFAIL1)XOSCFAIL1 0 (DFLLRDY)DFLLRDY 0 (DFLLOOB)DFLLOOB 0 (DFLLLCKF)DFLLLCKF 0 (DFLLLCKC)DFLLLCKC 0 (DFLLRCS)DFLLRCS 0 (DPLL0LCKR)DPLL0LCKR 0 (DPLL0LCKF)DPLL0LCKF 0 (DPLL0LTO)DPLL0LTO 0 (DPLL0LDRTO)DPLL0LDRTO 0 (DPLL1LCKR)DPLL1LCKR 0 (DPLL1LCKF)DPLL1LCKF 0 (DPLL1LTO)DPLL1LTO 0 (DPLL1LDRTO)DPLL1LDRTO

Description

Interrupt Enable Set

Fields

XOSCRDY0

XOSC 0 Ready Interrupt Enable

XOSCRDY1

XOSC 1 Ready Interrupt Enable

XOSCFAIL0

XOSC 0 Clock Failure Detector Interrupt Enable

XOSCFAIL1

XOSC 1 Clock Failure Detector Interrupt Enable

DFLLRDY

DFLL Ready Interrupt Enable

DFLLOOB

DFLL Out Of Bounds Interrupt Enable

DFLLLCKF

DFLL Lock Fine Interrupt Enable

DFLLLCKC

DFLL Lock Coarse Interrupt Enable

DFLLRCS

DFLL Reference Clock Stopped Interrupt Enable

DPLL0LCKR

DPLL0 Lock Rise Interrupt Enable

DPLL0LCKF

DPLL0 Lock Fall Interrupt Enable

DPLL0LTO

DPLL0 Lock Timeout Interrupt Enable

DPLL0LDRTO

DPLL0 Loop Divider Ratio Update Complete Interrupt Enable

DPLL1LCKR

DPLL1 Lock Rise Interrupt Enable

DPLL1LCKF

DPLL1 Lock Fall Interrupt Enable

DPLL1LTO

DPLL1 Lock Timeout Interrupt Enable

DPLL1LDRTO

DPLL1 Loop Divider Ratio Update Complete Interrupt Enable

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